Specifications

24-bit sigma delta codec (ADC, DAC), 36 kHz sample rate
Single channel input
Gain switchable pre-amplifier, 0 dB and 14 dB
Input impedance: 500 kΩ
Output: audio power amplifier, 250 mW per channel of continuous average power to an 8X load
with 0.1% (THD).
Full scale input/output voltage range, V (peak-to-peak), typical: ±1.8 V
Noise: <1 mV RMS, codec sample rate of 36 kHz
System latency, bypass: 0.68 milliseconds
System latency, IR: 1.80 milliseconds

Processor system

Clock Speed: 200 MHz
Enhanced Filter Co-Processor (EFCOP)
400 MMAC
24-bit resolution (56-bit intermediate)
Highly parallel instruction set with unique DSP addressing modes
Two 56-bit accumulators including extension byte
Two parallel 24 X 24-bit multiply-accumulates in 1 instruction cycle (1 clock cycle)
Double precision 48 X 48-bit multiply with 96-bit result in 6 instruction cycles
56-bit addition/subtraction in 1 instruction cycle
Fractional arithmetic with support for multi-precision arithmetic
Hardware support for block-floating point FFT
Hardware nested DO loops
Digital Phase Locked Loop (PLL) clock multiplier